A 10-bit 200MS/s Pipeline A/D Converter for High-Speed Video Signal Digitizer

Author

Nezuka, Tomohiro ; Misawa, Katsuhiko ; Azami, Junichiro ; Majima, Yusuke ; Okamura, Jun-ichi

Author_Institution

THine Electron., Inc., Tokyo

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

31

Lastpage

34

Abstract

A 10-bit 200MS/s A/D converter (ADC) for highspeed video signal digitizer is presented. The ADC has a 14- bit pipeline ADC core for digital programmable gain control and a reference voltage buffer optimized for high-speed A/D conversion. The ADC is fabricated in a 0.18-mum multiple Vth CMOS process. The area of ADC core is 1.15 mmtimes0.69 mm, and power consumption is 128 mW@200 MS/s. The measured INL and DNL are 1.05 LSB and 0.55 LSB respectively. The measured SNR and SFDR are 54.8 dB and 63.2 dB respectively.

Keywords

CMOS integrated circuits; analogue-digital conversion; buffer circuits; high-speed integrated circuits; signal processing equipment; video signal processing; ADC fabrication; CMOS process; DNL value; INL value; SFDR value; SNR value; digital programmable gain control; high-speed A/D conversion; high-speed video signal digitizer; optimized reference voltage buffer; pipeline A/D converter; power 128 mW; power consumption; size 0.18 mum; word length 10 bit; CMOS process; Capacitors; Circuits; Differential amplifiers; Dynamic range; Gain control; Operational amplifiers; Pipelines; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357844

Filename

4197583