A 58–63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS

This paper proposes a 60 GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise as low as -106 dBc/Hz using tail feedback to improve the phase noise. The proposed 60GHz ILO uses a combination of parallel and tail injection to enhance the locking range by reducing the Injection Locked Oscillator (ILO) current at the moment of injection. Both the 20 GHz PLL and the ILO were fabricated using a 65 nm CMOS process and measurement results show a phase noise of -96 dBc/Hz at 60 GHz while consuming 77.5 mW from a 1.2V supply. To to author´s knowledge this phase noise is about 20 dB better then recently reported QPLL and about 10 dB compared to düTerential PLL operating at similar frequency.