Fast technology mapping for multiplexor-based architecture with area/delay tradeoff

The authors present enhancements for a BDD-based approach to mapping Boolean networks multiplexor-based architectures like a FPGA by Actel. The algorithm combines the following: transformation of the Boolean network into a mixed BDD/ITE-description, an area-delay tradeoff and effective tree-pruning using a large library. The algorithm performs several times faster than state-of-the-art approaches while delivering competitive results. Its intended usage is the frequent evaluation of the necessary chip area for a given set of Boolean functions in a logic minimization tool