High level testability analysis using VHDL descriptions

Author

Vishakantaiah, Praveen ; Abraham, Jacob A.

Author_Institution

Comput Eng. Res. Center, Univ. of Texas, Austin, TX, USA

fYear

1993

fDate

22-25 Feb 1993

Firstpage

170

Lastpage

174

Abstract

Tests generated for modules in a design may not be applicable from the design boundaries due to global constraints. The authors discuss high level techniques that can be used to analyze a sequential circuit and precompute useful information that reflects the controllability of inputs and observability of outputs of modules in the design. The information can then be used in conjunction with the tests generated for modules to obtain high quality tests for the design quickly. Results obtained for example circuits are presented to demonstrate the techniques

Keywords

design for testability; hardware description languages; high level synthesis; logic testing; sequential circuits; VHDL descriptions; controllability of inputs; high level testability analysis; modules; observability of outputs; sequential circuit; test knowledge generation; Art; Assembly; Automatic test pattern generation; Circuit faults; Circuit testing; Performance analysis; Performance evaluation; Sequential analysis; Switches; Synchronous generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386481

Filename

386481