DocumentCode
2560900
Title
Partial reset: An inexpensive design for testability approach
Author
Mathew, Ben ; Saab, Daniel G.
Author_Institution
Coordinated Sci. Lab., Univ. of Illinois, Urbana, IL, USA
fYear
1993
fDate
22-25 Feb 1993
Firstpage
151
Lastpage
155
Abstract
A design for testability (DFT) method called partial reset is studied. Reset lines are added to a subset of the flip-flops. partial reset improves the fault coverage of sequential circuit, on the average, by 15% over the fault coverage of the original circuit. This approach has lower overhead in terms of test application time and hardware area when compared to scan techniques. This method has been tested on the 1989 ISCAS sequential benchmark circuits and favorable results have been obtained
Keywords
VLSI; design for testability; logic CAD; logic testing; sequential circuits; ISCAS 89 sequential benchmarks; VLSI; fault coverage; inexpensive design for testability; observability improvement; partial reset; sequential circuit; Circuit faults; Circuit testing; Design for testability; Flip-flops; Hardware; Logic testing; Observability; Routing; Sequential analysis; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location
Paris
Print_ISBN
0-8186-3410-3
Type
conf
DOI
10.1109/EDAC.1993.386484
Filename
386484
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