Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications

Self refresh current in modern DRAMs is becoming more difficult problem to handle because the decreasing cell transistor size has a negative effect on the uniformity of capacitor charge. In order to solve this issue, adaptive self refresh(ASR) scheme has been developed. A dual period based refresh is performed in the ASR scheme to reduce power dissipation using row register information. The row register information is adaptively modified according to the cell data retention characteristics. When DRAM enters self refresh mode, only the rows which were activated for write are tested using internal refresh test circuits. The test results are used to choose the appropriate period for the dual period base self refresh operation. This paper demonstrates 512M mobile SDRAM utilizing this adaptive self refresh(ASR) capability to minimize standby power to 150 uA @85degC while maintaining chip area of the conventional scheme using the same process technology.