New concepts for IT-DRAMs: Overcoming the scaling limits

Author

Rodríguez, Noel ; Cristoloveanu, Sorin ; Gámiz, Francisco

Author_Institution

Dept. Electron. y Tecnol. de Comput., Univ. of Granada, Granada, Spain

Volume

1

fYear

2011

fDate

17-19 Oct. 2011

Firstpage

11

Lastpage

14

Abstract

Capacitorless Single-Transistor DRAM cells (IT-DRAM) are attractive for the replacement of the highly complex standard DRAM cells based on the combination of a transistor and a capacitor. However, their implementation is questioned mainly due to scalability concerns in ultrathin silicon films. In this paper, we will present new concepts of IT-DRAM memory cells based on multi-body architectures that are able to fulfil the scalability requirements of advanced technology nodes. The proposed devices, belonging to the A-RAM family, feature enhanced resolution between `0´ and `1´ states as well as very low bias operation.

Keywords

DRAM chips; elemental semiconductors; integrated circuit reliability; silicon; thin films; A-RAM family; IT-DRAM memory cells; Si; capacitorless single-transistor DRAM cells; multibody architectures; scalability requirements; scaling limits; ultrathin films; very low bias operation; Charge carrier processes; Electric fields; Logic gates; Random access memory; Silicon; Silicon on insulator technology; Transistors; A-RAM; A2RAM; Floating-Body; IT-DRAM; Supercoupling;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2011 International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-61284-173-1

Type

conf

DOI

10.1109/SMICND.2011.6095698

Filename

6095698