An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm

Author

Choi, Youngdon ; Jeong, Deog-Kyoon ; Kim, Wonchan ; Lee, Jung-Bae ; Kim, Chang-Hyun

Author_Institution

Seoul Nat. Univ., Seoul

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

383

Lastpage

386

Abstract

This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10^-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.

Keywords

CMOS integrated circuits; error statistics; integrated circuit design; integrated circuit manufacture; integrated circuit noise; probability; receivers; CMOS technology; LVDS receiver; bit error rate; bit rate 1.4 Gbit/s; boundary-based tracking algorithm; flat panel display; high-speed link; jitter distribution; jitter probability density function; jitter-boundary-based digitally controlled de-skewing algorithm; memory system; power 381 mW; size 0.25 mum; time 87.9 ps; Bit error rate; CMOS technology; Control systems; Delay; Digital control; Flat panel displays; Jitter; Probability density function; Sampling methods; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357931

Filename

4197670