Design of a low noise readout ASIC for CdZnTe detector

A low noise readout ASIC has been designed for CdZnTe detector. This chip contains 16 channels and each channel consists of a dual-stage charge sensitive preamplifier, 4^th order semi-Gaussian shaper, leakage current compensation circuit (LCC), discriminator and output buffer. This chip has been fabricated in Globalfoudries 0.35 μm CMOS process, the preliminary results are presented here. The total channel charge gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μS to 4 μS. The minimum ENC at zero input capacitance measured at maximum charge gain and 1.33 μS peaking time is 70 e. The noise difference between FR4 and PTFE test board are analyzed. When connected with a 4 × 4 pixelated CdZnTe detector, energy spectrum from radioactive isotope has been measured with energy resolution of 2.74 keY FWHM for ²⁴¹Am.