DocumentCode
2562896
Title
Cell Merge: A basic-pre-clustering clustering algorithm for placement
Author
Zhang, Xin ; Takeuchi, Tsuyoshi ; Toyonaga, Masahiko
Author_Institution
Fac. of Sci., Kochi Univ., Kochi, Japan
fYear
2009
fDate
18-20 May 2009
Firstpage
47
Lastpage
50
Abstract
In DSM era, digital circuits can contain millions placeable elements, and the complexity and the size of circuits have grown exponentially. For reducing the circuit sizes, clustering algorithm have become popular, so that the placement process can be performed faster and with higher quality. In this paper, we proposed a novel basic-pre-clustering clustering algorithm called Cell Merge which can reduce effectively the circuit size. The algorithm has proven a linear-time complexity of O(n), where n is the number of nets in a circuit. The numerical experiments on ISPD02 IBM-MS mixed-size benchmark suite for placement show that by applying Cell Merge as a processing step, the performance of state-of-the-art placer can be further improved.
Keywords
VLSI; circuit CAD; circuit complexity; computational complexity; digital integrated circuits; pattern clustering; basic-pre-clustering clustering algorithm; cell merge; circuit complexity; circuit size; linear time complexity; Algorithm design and analysis; Clustering algorithms; Delay; Digital circuits; Integrated circuit interconnections; Integrated circuit technology; Partitioning algorithms; Runtime; Statistics; Very large scale integration; clustering; partitioning; physical design; placement; very large scale integration (VLSI);
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-2933-2
Electronic_ISBN
978-1-4244-2934-9
Type
conf
DOI
10.1109/ICICDT.2009.5166262
Filename
5166262
Link To Document