Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.