DocumentCode
2563720
Title
Memory Performance and Scalability of Intel´s and AMD´s Dual-Core Processors: A Case Study
Author
Peng, Lu ; Peir, Jih-Kwon ; Prakash, Tribuvan K. ; Chen, Yen-Kuang ; Koppe, David
Author_Institution
Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA
fYear
2007
fDate
11-13 April 2007
Firstpage
55
Lastpage
64
Abstract
As chip multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, performance studies on an Intel Core 2 Duo, an Intel Pentium D and an AMD Athlon 64times2 processor are reported. According to the design specifications, key derivations exist in the critical memory hierarchy architecture among these dual-core processors. In addition to the overall execution time and throughput measurement using both multiprogrammed and multi-threaded workloads, this paper provides detailed analysis on the memory hierarchy performance and on the performance scalability between single and dual cores. Our results indicate that for the best performance and scalability, it is important to have (1) fast cache-to-cache communication, (2) large L2 or shared capacity, (3) fast L2 to core latency, and (4) fair cache resource sharing. Three dual-core processors that we studied have shown benefits of some of these factors, but not all of them. Core 2 Duo has the best performance for most of the workloads because of its microarchitecture features such as shared L2 cache. Pentium D shows the worst performance in many aspects due to its technology-remap of Pentium 4.
Keywords
cache storage; microprocessor chips; AMD Athlon 64; Intel Core 2 Duo; Intel Pentium D; cache-to-cache communication; chip multiprocessor; dual-core processors; fair cache resource sharing; Bandwidth; Computer architecture; Delay; Information science; Manufacturing; Measurement; Memory architecture; Scalability; Testing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance, Computing, and Communications Conference, 2007. IPCCC 2007. IEEE Internationa
Conference_Location
New Orleans, LA
ISSN
1097-2641
Print_ISBN
1-4244-1138-6
Electronic_ISBN
1097-2641
Type
conf
DOI
10.1109/PCCC.2007.358879
Filename
4197915
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