DocumentCode
2563932
Title
Calculating worst-case gate delays due to dominant capacitance coupling
Author
Dartu, Florentin ; Pileggi, Lawrence T.
fYear
1997
fDate
9-13 June 1997
Firstpage
46
Lastpage
51
Keywords
Capacitors; Delay lines; Dielectrics; Equations; Integrated circuit noise; Parasitic capacitance; Permission; Predictive models; Semiconductor device noise; Thickness control;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-7803-4093-0
Type
conf
DOI
10.1109/DAC.1997.597115
Filename
597115
Link To Document