A fault simulation method for crosstalk faults in synchronous sequential circuits

With the scaling down of VLSI size and the reducing switching time of logic gates, crosstalk faults become an important problem for testing. If a crosstalk pulse is excited by internal noise sources, the crosstalk pulse tends to be considered as harmless for synchronous sequential circuits, because generated crosstalk pulses on data lines can be eliminated by a clocking. However the crosstalk pulse generated on clock lines or reset lines can lead the circuit to erroneous operations. We analyze the crosstalk fault scheme, and contrive a fault simulator based on the scheme, in order to estimate the effect for the crosstalk fault. We consider the crosstalk fault as unexpected strong capacitive coupling between one data line and clock lines. Since we have to consider timing in addition to a logic value, a unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates are widely varied corresponding to circuit characteristics. Up to 80% fault detection rates are obtained from our simulation with test vectors generated at random