A single-chip, functional tester for VLSI circuits

Author

Gasbarro, J.A. ; Horowitz, M.A.

Author_Institution

Xerox Palo Alto Res. Center, CA, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

84

Lastpage

85

Abstract

A single-chip functional tester for VLSI circuits that integrates the vector memory, the error memory, a decompressor, and 16 sets of independently controlled pin electronics on a 9.0*9.4-mm chip is described. The device contains over 200 K transistors and is fabricated using a 1.6- mu m CMOS technology. The integrated pin electronics support a per-pin tester architecture, allowing the transitions for each pin to be independently adjusted to better than 1 ns. The chip dissipates less than 0.75 W running at 25 M vectors/s. By integrating all tester functions on a single chip, it is possible to build all extremely compact tester. A 256-pin tester requires only 16 chips. This size makes it possible to reduce the length of the transmission line between the device under test and the tester to under 10 cm, minimizing signal reflections and enabling the delivery of high-fidelity waveforms.<>

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; integrated circuit testing; test equipment; 1.6 micron; CMOS technology; VLSI circuits; decompressor; error memory; functional tester; high-fidelity waveforms; per-pin tester architecture; signal reflections; transmission line; vector memory; CMOS technology; Circuit testing; Delay lines; Electronic equipment testing; Pins; Propagation delay; Random access memory; Space vector pulse width modulation; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110140

Filename

110140