A CMOS switched-current filter technique

Author

Fiez, T.S. ; Allstot, David J.

Author_Institution

Oregon State Univ., Corvallis, OR, USA

fYear

1990

fDate

14-16 Feb. 1990

Firstpage

206

Lastpage

207

Abstract

Basic design techniques and considerations for switched-current (SI) circuits are presented, and experimental results from integrated filters are given. By means of analogies to switched-capacitor circuits, a five-pole lowpass Chebyshev SI filter has been integrated in a 2- mu m N-well, double-metal CMOS technology. The average die area is about 200 mil/sup 2/ per SI pole. The current mirror gain factors were derived by means of signal flow-graph techniques starting with the RLC prototype. A doubly terminated five-pole Chebyshev filter was designed for a 0.1-dB ripple bandwidth of 5 kHz with a sampling frequency of 128 kHz. The measured response is shown. The noise floor is about 70 dB down with respect to the passband. A three-pole elliptic SI filter has also been integrated to illustrate the realization of transmission zeros with SI filter techniques.<>

Keywords

CMOS integrated circuits; active filters; linear integrated circuits; low-pass filters; switched filters; design techniques; double-metal CMOS technology; doubly terminated; five-pole Chebyshev filter; lowpass; n-well process; signal flow-graph techniques; switched-current filter; three pole elliptic filter; Band pass filters; CMOS analog integrated circuits; CMOS technology; Chebyshev approximation; Integrated circuit technology; Mirrors; Prototypes; RLC circuits; Switched capacitor circuits; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Conference_Location

San Francisco, CA, USA

Type

conf

DOI

10.1109/ISSCC.1990.110197

Filename

110197