• DocumentCode
    2566914
  • Title

    A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support

  • Author

    Golden, M. ; Arekapudi, S. ; Dabney, G. ; Haertel, M. ; Hale, S. ; Herlinger, L. ; Kim, Youngjae ; McGrath, Kevin ; Palisetti, V. ; Singh, Monika

  • Author_Institution
    Adv. Micro Devices, Sunnyvale, CA
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    325
  • Lastpage
    332
  • Abstract
    A microprocessor featuring 2 Hammer cores and an on-chip DDR2 memory controller implements Pacifica architectural support for virtualization. It is fabricated in a 90nm triple-Vt partially-depleted SOI process with 9 layers of copper interconnect. The chip achieves a clock frequency of 2.6GHz at 1.35V while dissipating 95W
  • Keywords
    DRAM chips; copper; integrated circuit interconnections; microprocessor chips; system-on-chip; 1.35 V; 2.6 GHz; 90 nm; 95 W; DDR2 memory controller; Pacifica architectural support; copper interconnect; microprocessor; partially-depleted SOI process; virtualization; Clocks; Control systems; Copper; Frequency; Logic arrays; Microprocessors; Repeaters; Routing; Signal design; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696063
  • Filename
    1696063
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2566914