DocumentCode

2567939

Title

Exact Required Time Analysis Via False Path Detection

Author

Kttkimoto, Y. ; Brayton, Robert K.

Author_Institution

Department of Electrical Engineering and Computer Sciences, University of California

fYear

1997

fDate

9-13 June 1997

Firstpage

220

Lastpage

225

Keywords

Automatic logic units; Circuit synthesis; Circuit testing; Computer networks; Delay; Logic testing; Network synthesis; Permission; Power dissipation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the 34th

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-7803-4093-0

Type

conf

DOI

10.1109/DAC.1997.597147

Filename

597147