Design of a small-area current steering CMOS D/A converter based on a novel layout technique

Author

Song, Minkyu

Author_Institution

Dongguk Univ., Seoul

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

273

Lastpage

276

Abstract

A 12 - b 300 MSPS current-steering DAC with 0.13 um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26 mm² even in 12 -b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12- b DAC performance. The measured results are within plusmn1LSB for DNL. The measured SFDR is 70 dB under Nyquist output frequency with 50 mW power dissipation at 3.3V power supply.

Keywords

CMOS analogue integrated circuits; digital-analogue conversion; CMOS technology; current autoaveraging technique; current steering CMOS D/A converter; laminated-step layout technique; latched switching cell logic; output impedance enhancement circuit; power 50 mW; size 0.13 micron; voltage 3.3 V; CMOS logic circuits; CMOS process; CMOS technology; Decoding; Impedance; Logic circuits; Operational amplifiers; Power measurement; Routing; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415620

Filename

4415620