DocumentCode
2568243
Title
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13/spl mu/m CMOS
Author
Nogawa, Masafumi ; Ohtomo, Y. ; Kimura, Shunji ; Nishimura, Kosuke ; Kawamura, Toshihiko ; Togashi, Minoru
Author_Institution
NTT, Atsugi
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
940
Lastpage
949
Abstract
A 10Gb/s burst-mode limiting amplifier is developed in a 0.13mum CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s
Keywords
CMOS integrated circuits; pulse amplifiers; radio receivers; 0.13 micron; 0.8 ns; 10 Gbit/s; CMOS integrated circuit; adaptive gain limiting amplifier; adaptive gain-selection technique; burst-mode limiting amplifier; CMOS integrated circuits; Delay; Detectors; Dynamic range; Ethernet networks; Hysteresis; Passive optical networks; Semiconductor device measurement; Signal detection; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696135
Filename
1696135
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