• DocumentCode
    2568933
  • Title

    A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

  • Author

    Tokunaga, Yo ; Sakiyama, S. ; Dosho, S. ; Doi, Yoshihito ; Hattori, Masashi

  • Author_Institution
    Matsushita Electr. Ind., Moriguchi
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    1286
  • Lastpage
    1295
  • Abstract
    A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to 300MHz, consumes 9mW from a 2 to 4V supply, and occupies 0.03mm2 in a 0.30mum CMOS process
  • Keywords
    CMOS integrated circuits; digital phase locked loops; peripheral interfaces; phase detectors; 0.30 micron; 2 to 4 V; 20 to 300 MHz; 9 mW; CMOS process; DDR interface; duty-cycle correction; false-lock free DLL; fully balanced charge-pump; phase detector; reduced update noise; Active filters; Charge pumps; Circuits; Clocks; Delay; Jitter; Partial discharges; Timing; Virtual colonoscopy; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696176
  • Filename
    1696176
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2568933