Scheduling on a superscalar processor using the chain technique

Instruction level parallelism is one of the basic ways of increasing the performance of current processors. One method to improve instruction parallelism is the chain technique, which bypasses execution results from one Arithmetic Logic Unit (ALU) to others. However, this technique cannot be used with the current superscalar processor scheduling method. We develop a scheduling method for the chain technique that uses a dependence map. Experimental results show that the proposed method can be effectively used with the chain technique to improve the IPC. The Instructions Per Clock (IPC) can also be improved by reducing the number of instruction window entries.