Power efficient high speed switched current comparator

A power efficiency improved switched current comparator based on Boonsobhak´s comparator is presented. Controlled by two complementary clock signals, the proposed comparator operates in a master and slave manner. The master comparator not only generates a voltage difference according to the input current, but also isolate the input terminal from the output signals to prevent extreme voltage surge, or kickback noise, while the slave comparator is allowed to regenerate and produce a valid digital output. Employing a static class AB latched comparator as the master comparator and a O-static-power-dissipated dynamic latched comparator as the slave one; the proposed current comparator achieves high power efficiency and high speed. Designed and simulated in TSMC 0.25 m mixed signal CMOS technology with 1.8 V supply voltage, the proposed SI comparator achieves a current sensitivity up to 0.2 muA, and a sampling frequency up to 400 MHz, with 30% power reduction compared to the original one.