DocumentCode
2570627
Title
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS
Author
Plouchart, Jean-Olivier ; Kim, Jonghae ; Karam, Victor ; Trzcinski, Robert ; Gross, Jeff
Author_Institution
IBM, Hopewell Junction, NY
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
2142
Lastpage
2151
Abstract
A 66GHz maximum operating clock frequency is measured for a 90nm CMOS static CML divide-by-2 with a 25.5mW latch power dissipation. Statistical self-oscillation frequency measurements exhibit a mean of 42.6 and 39.2GHz at 25degC and 85degC, and a 2.8GHz standard deviation. The mean dissipated power is 44.3mW at 1.4V, with a 2.2mW standard deviation
Keywords
CMOS logic circuits; clocks; current-mode logic; frequency dividers; millimetre wave frequency convertors; 1.4 V; 2.2 mW; 2.8 GHz; 25 C; 25.5 mW; 39.2 GHz; 42.6 GHz; 44.3 mW; 66 GHz; 85 C; 90 nm; CMOS integrated circuits; current mode logic; latch power dissipation; static CML divider; statistical self-oscillation; CMOS digital integrated circuits; CMOS technology; Capacitors; Delay; Frequency conversion; Integrated circuit technology; Millimeter wave integrated circuits; Millimeter wave technology; Phase shifters; Radiofrequency integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696274
Filename
1696274
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