DocumentCode
2570926
Title
Neurons to Silicon: Implantable Prosthesis Processor
Author
O´Driscoll, Stephen ; Meng, Teresa ; Shenoy, Krishna ; Kemere, Caleb
Author_Institution
Stanford Univ., CA
fYear
2006
fDate
6-9 Feb. 2006
Firstpage
2248
Lastpage
2257
Abstract
A processor architecture for neural prosthesis control is described. It implements real-time neural decoding from a permanently implanted electrode array to reduce the data rate from 80Mb/s to 20b/s, minimizing the wireless communication requirements. The neural signals are digitized by a 100-channel 100kS/s adaptive-resolution ADC array consuming 1muW per channel
Keywords
analogue-digital conversion; biomedical electrodes; microprocessor chips; neural chips; prosthetics; adaptive-resolution ADC array; analog-to-digital converters; implantable prosthesis processor; implanted electrode array; neural decoding; neural prosthesis control; neural signals; processor architecture; wireless communication; Data mining; Energy consumption; Energy resolution; MIM capacitors; Neural prosthesis; Neurons; Parasitic capacitance; Prosthetics; Signal processing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0079-1
Type
conf
DOI
10.1109/ISSCC.2006.1696287
Filename
1696287
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