• DocumentCode
    2571903
  • Title

    A fast-simulation model for post-layout SRAM

  • Author

    Jing, Xiaocheng ; Yao, Ruohe

  • Author_Institution
    South China Univ. of Technol., Guangzhou
  • fYear
    2007
  • fDate
    22-25 Oct. 2007
  • Firstpage
    1197
  • Lastpage
    1200
  • Abstract
    A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.
  • Keywords
    random-access storage; microprocessor chips; post-layout SRAM; post-layout static random access memory; transistor-level simulation; Circuit simulation; Clocks; Decoding; Parameter extraction; Physics; Random access memory; SRAM chips; Signal generators; Timing; Transistors; SRAM; XRC; fast-simulation Model; layout; transistor-level simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2007. ASICON '07. 7th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4244-1132-0
  • Electronic_ISBN
    978-1-4244-1132-0
  • Type

    conf

  • DOI
    10.1109/ICASIC.2007.4415849
  • Filename
    4415849
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2571903