A two-mode debugging system for VLSI designs using Xilinx FPGA

Increasingly complicated VLSI design or system-on-chip (SOC) makes FPGA-based emulation necessary. As a design is downloaded into a FPGA-based emulator, invisible internal nodes of the design pose a challenge for design debugging. A debugging system is proposed to address the issue. An RTL-level runtime debugging method is utilized in the system. The user can not only select sampling signals, triggering signal and statement in RTL codes, but can change triggering mode or sampling window runtime as well. This debugging system supports two debugging modes including both scan mode and snapshot mode. In the proposed debugging system, communication channel is provided for Xilinx FPGA. Experiment results show that compared with ChipScope, scan mode and snapshot mode consumes fewer resources.