Leakage aware design for next generation’s SOCs

We describe basic design techniques, that have proven to hold great potential for leakage optimization in practical design environments. They range from gate/circuit level (e.g. dual Vth, MTCMOS, sleep transistor insertion), to memory blocks (e.g. array partitioning, sub-banking, bit line splitting, cache decay, drowsy state memory, exploit locality, etc) and architectural styles (e.g. region-based adaptive Vdd and Body Biasing, Vth hopping, Power gating, etc.). A selection of significative industrial solutions obtained by the application of low-power techniques to proprietary designs covering different application domains (including high-performance microprocessors, memory/cache structure and hardware platforms for embedded multi-media processing) will be reported as well.