Performance of dynamically scheduling VLIW instructions

Author

Jee, Sunghyun ; Palaniappan, Kannappan

Author_Institution

Dept. of Comput. Inf., Chonan Coll. in Foreign Studies, Chungnam, South Korea

fYear

2003

fDate

19-21 Nov. 2003

Firstpage

7

Lastpage

10

Abstract

This paper evaluates performance of the dynamically instruction scheduled VLIW (DISVLIW) processor architecture. The DISVLIW processor architecture is designed for dynamically scheduling VLIW instructions using dependency information. Features such as explicit parallelism, balanced scheduling effort, and dynamic scheduling of VLIW instructions can be used to provide a sound structure for supercomputing. We simulate the DISVLIW processor architecture and show that the DISVLIW processor performs significantly better than the VLIW processor across various numerical benchmark applications.

Keywords

dynamic scheduling; instruction sets; microprocessor chips; parallel architectures; performance evaluation; DISVLIW; VLIW instructions; VLIW processor; balanced scheduling effort; benchmark applications; dependency information; dynamic scheduling; dynamically instruction scheduled VLIW; explicit parallelism; performance evaluation; processor architecture; supercomputing; Computer architecture; Computer science; Dynamic scheduling; Educational institutions; Modems; Packaging; Parallel processing; Process design; Processor scheduling; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip, 2003. Proceedings. International Symposium on

Print_ISBN

0-7803-8160-2

Type

conf

DOI

10.1109/ISSOC.2003.1267703

Filename

1267703