A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operation

A novel 6T-SRAM cell layout designed with rectangular patterns has been developed. Employing this layout, 4.13 /spl mu/m/sup 2/ and 5.33 /spl mu/m/sup 2/ cells with word transistor width of 0.25 /spl mu/m and 0.75 /spl mu/m are obtained, respectively, based on the 0.20 /spl mu/m rule. Among the various layouts of 6T-SRAM cells, this layout provides minimum cell size and the smallest bit line capacitance with word transistor width over 0.75 /spl mu/m for the ultra high speed operation. It is also demonstrated quantitatively that the optimized SRAM cell layout for high speed use is different from that for low power use. The cell layout proposed also provides the excellent scalability beyond 0.18 /spl mu/m generation due to its highly simplified pattern design.