A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

Author

Ootsuka, F. ; Nakamura, M. ; Miyake, T. ; Iwahashi, S. ; Ohira, Y. ; Tamaru, T. ; Kikushima, K. ; Yamaguchi, K.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1998

fDate

6-9 Dec. 1998

Firstpage

205

Lastpage

208

Abstract

An SRAM cell is proposed, in which additional capacitance is formed between the two local interconnects which are used for cross couple wiring. This novel cell with stacked cross couple (SCC) has an advantage in reducing the cell area to 80% of that of the conventional SRAM cell. Furthermore, the capacitor area can be enlarged to 40% of the cell area which enables one to adopt thick capacitor insulator. Reduction in capacitor leakage current by using plasma SiN with low Si-H concentration, and the device performances are also discussed.

Keywords

CMOS memory circuits; SRAM chips; errors; integrated circuit interconnections; 0.20 micron; CMOS SRAM cell; SiN; capacitance; capacitor; interconnect wiring; leakage current; plasma SiN insulator; soft error immunity; stacked cross couple; BiCMOS integrated circuits; CMOS process; Capacitance; Capacitors; Coupling circuits; Error correction; Error correction codes; Integrated circuit interconnections; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-4774-9

Type

conf

DOI

10.1109/IEDM.1998.746324

Filename

746324