A 3-dimension topology generation approach for networks-on-chip

A 3-dimension topology generation approach based Spidergon is proposed. The approach determines the structure of topology by the relationship between delay model and number of layers, which based on the prototype topology. Furthermore, a adaptive routing algorithm is proposed. This routing algorithm routed packets in vertical direction firstly, and improve the throughput by finding the equivalent shortest path. The experiment shows that the proposed topology achieves the reduction of 17% and the promotion of 16.7% compared with 3D-Mesh in the same scale.