DocumentCode
2576436
Title
Synthesis method for switched-capacitor FIR decimators and interpolators
Author
Betts, A.K. ; Taylor, J.T. ; Haigh, D.G.
Author_Institution
Univ. Coll., London, UK
fYear
1988
fDate
7-9 June 1988
Firstpage
2463
Abstract
A method is given for the systematic synthesis of FIR (finite-impulse-response) switched-capacitor decimation and interpolation filters that includes the derivation of an optimum clocking scheme. The latter allows the maximum possible settling times for the operational amplifiers (OAs), thus minimizing response errors associated with finite OA slew-rate and bandwidth. An example, in which the time allowed for OA settling in a published circuit is increased by considerable factors, is given.<>
Keywords
active filters; interpolation; network synthesis; network topology; switched capacitor filters; SC filters; active filters; circuit topology; finite-impulse-response; interpolation filters; op amp settling time; operational amplifiers; optimum clocking scheme; switched-capacitor FIR decimators; systematic synthesis; Capacitors; Circuits; Clocks; Delay; Educational institutions; Finite impulse response filter; Frequency; Interpolation; Sampling methods; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15441
Filename
15441
Link To Document