The Method of Making Low-cost Multiple-Row QFN

QFN demand has dramatically increased during the past 3 years. It has been replacing older packages like SOIC and TSSOP mainly because of the added thermal enhancements from the exposed pad, as well as the elimination of coplanarity issues. QFN is also being chosen for next- generation packages because it has a relatively bigger pad size, allowing more flexibility in accommodating bigger die size, die integration and the added advantage of thermal enhancement. However, as the package requires more I/O in a smaller footprint, current QFN structure will have some limitations. Currently, there is a solution for two rows of I/O but any higher than that, the available solution becomes more expensive - one solution requires laser cutting to isolate each row and another requires use of photo-imaging, develop and etching process to define the I/O. This paper describes an alternative methodology for making a low-cost QFN with multiple rows. The leadframe raw material that will be used will be solid copper, half etched on one side, with selective silver plating. The difference from existing QFN leadframes is that this does not need tape during molding. There will be two new processes introduced: selective copper etching and electroless plating. Although these processes are commonly used in other industries, the challenges and proposed solutions encountered in adopting them in IC packaging assembly will be discussed. Apart from the cost advantage, manufacturing and performance advantages and disadvantages related to these new methods will also be tackled.