3D simulation of the effect of e-beam lithography induced line-edge roughness on 50 nm NMOS Id-Vg characteristics

Author

Scheiblin, P. ; Foucher, J.

Author_Institution

CEA-DRT-LETI, Grenoble, France

fYear

2003

fDate

29-31 Oct. 2003

Firstpage

242

Lastpage

243

Abstract

3D simulation results on effects induced by e-beam lithography line-edge roughness (LER) in the case of a 50 nm NMOS were presented. It was shown that 3D simulation is mandatory to describe electrical characteristics when the minimum of the gate length reached approximately 30 nm, due to LER. Otherwise, the 3D transistor is equivalent to a 2D transistor, indicating weak 3D effects.

Keywords

MOSFET; electron beam lithography; semiconductor device models; 2D transistor; 30 nm; 3D simulation; 3D transistor; 50 nm; NMOS; electrical properties; electron beam lithography; gate length; line edge roughness; Anisotropic magnetoresistance; Circuit optimization; Etching; Fluctuations; Geometrical optics; Lithography; MOS devices; Pattern analysis; Resists; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocesses and Nanotechnology Conference, 2003. Digest of Papers. 2003 International

Conference_Location

Tokyo, Japan

Print_ISBN

4-89114-040-2

Type

conf

DOI

10.1109/IMNC.2003.1268736

Filename

1268736

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2580799