A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform

Novel online algorithms and architectures for hierarchical coding using the wavelet transform are presented. These algorithms/architectures compute the decomposition-reconstruction cycle of the wavelet transform with minimum latency and buffering for any given blocking factor. A hierarchical scheme which enables cheap video conferencing and/or multicast over a heterogeneous network is also presented. This architecture supports single chip implementations of the encoder, the decoder, and the transcoder for some choices of the wavelet filter and vector quantization schemes