Designing reusable components in VHDL

Hardware Description Languages (HDLs) are commonly used to construct hardware systems. Reuse of the designs is common practice to improve the productivity. The HDLs allow the creation of reusable models, but design disciplines are required to reach an efficient reusable design, because the reusability of a design does not come with language features alone. Analysis of the reusability in VHDL applications may provide useful information to design methodologies. In this paper, the reusability issues and the design methodologies to achieve Design-For-Reusability (DFR) are summarized. The results of measuring the reusability of ten VHDL applications, based on the reusable models, are presented