A 35 GHz dual-loop PLL with low phase noise and fast lock for millimeter wave applications

Author

Gai, Xiaolei ; Chartier, Sébastien ; Trasser, Andreas ; Schumacher, Hermann

Author_Institution

Inst. of Electron Device & Circuits, Univ. of Ulm, Ulm, Germany

fYear

2011

fDate

5-10 June 2011

Firstpage

1

Lastpage

4

Abstract

A fully integrated dual-loop PLL for mm-wave applications is presented. The design includes a phase locked hold loop and a frequency acquisition loop; by using two types of phase detectors for each individual loop, a low phase noise, a fast lock time, and a wide locking range can be achieved simultaneously. A method for phase noise optimization of the PLL is described. The chip was designed in a 250 nm SiGe BiCMOS technology. The locking range is from 33.8 to 37.6 GHz. The output phase noise is around -106 dBc/Hz at 1MHz offset.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; III-V semiconductors; integrated circuit noise; millimetre wave circuits; phase detectors; phase locked loops; phase noise; BiCMOS technology; dual-loop PLL; frequency 33.8 GHz to 37.6 GHz; frequency acquisition loop; low phase noise; millimeter wave applications; phase locked hold loop; phase noise optimization; size 250 nm; Detectors; Frequency conversion; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators; Millimeter wave circuits; Phase locked loops; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International

Conference_Location

Baltimore, MD

ISSN

0149-645X

Print_ISBN

978-1-61284-754-2

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2011.5972664

Filename

5972664