DocumentCode
2582867
Title
Coupling aware routing
Author
Kastner, Ryan ; Bozorgzadeh, Elaheh ; Sarrafzadeh, Majid
Author_Institution
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
fYear
2000
fDate
2000
Firstpage
392
Lastpage
396
Abstract
In this paper, we develop methods to reduce interconnect delay and noise caused by coupling. First, we introduce two novel problems that deal with coupling-the Coupling-Free Routing (CFR) Problem and the Maximum Coupling-Free Layout (MAX-CFL) Problem. We argue that these problems are useful in both global and detailed routing. Then, we develop algorithms to efficiently solve the problems. Our experimental results show that the algorithms work effectively on real data
Keywords
VLSI; circuit layout CAD; delays; integrated circuit interconnections; integrated circuit layout; integrated circuit noise; network routing; VLSI layout; coupling aware routing; coupling-free routing problem; detailed routing; global routing; interconnect delay reduction; interconnect noise reduction; maximum coupling-free layout problem; Capacitance; Clocks; Coupling circuits; Delay; Fabrication; Integrated circuit interconnections; Noise reduction; Routing; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6598-4
Type
conf
DOI
10.1109/ASIC.2000.880770
Filename
880770
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