An improved Nelder-Mead method for analog design optimisation applied to deep sub-micron technology

Finding a good trade-off between contradictory specifications requires a certain amount of time and simulations. However, time, simulator licences and hardware resources are often limited. That is why design optimisers were developed, allowing to shorter design cycles. Nonetheless, their performance are often limited by the increasing complexity of the optimisation problem. This paper provides an efficient method to enhance designs based on an improved version of the Nelder-Mead algorithm. Its implementation was done in SKILL, a Lisp like programming language developed by Cadence. The results of high frequency Current Mode Logic (CML) chains realised in 20 nm technology illustrate its performance.