DocumentCode
2585794
Title
High Linearity Down-Conversion CMOS Mixers
Author
Manstretta, Danilo
Author_Institution
Dipt. di Elettron., Univ. degli Studi di Pavia, Pavia
fYear
2008
fDate
27-28 Oct. 2008
Firstpage
175
Lastpage
178
Abstract
This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300 kHz, 9 dBm IIP3 and 75 dBm minimum IIP2 while drawing 5.4 mA from a 1.2 V supply.
Keywords
CMOS integrated circuits; low-power electronics; mixers (circuits); network topology; bandwidth 10 kHz to 1.92 MHz; current 5.4 mA; frequency 300 kHz; high linearity down-conversion CMOS mixers; size 90 nm; voltage 1.2 V; 1f noise; CMOS technology; Circuit noise; Linearity; Noise figure; Radio frequency; Signal to noise ratio; Transconductance; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Integrated Circuit Conference, 2008. EuMIC 2008. European
Conference_Location
Amsterdam
Print_ISBN
978-2-87487-007-1
Type
conf
DOI
10.1109/EMICC.2008.4772257
Filename
4772257
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