Multi-core accelerated harmonic balance method for multi-tone full chip RFIC simulation

Harmonic balance (HB) method is a pure frequency domain simulation method. Harmonic balance works well for mildly nonlinear RF circuits; however, its performance can be a critical issue as the circuit size increases and the circuit nonlinearity becomes dominant. With the advent of multi-core computers, multi-threading (MT) technique is a good choice to improve efficiency of the traditional harmonic balance method. Since the harmonic balance simulation is very memory-bandwidth-bounded, it is hard to achieve a good MT performance when the CPU number is large. In this paper, we present a harmonic balance technique, with great MT scalability, for many-core computers. We implemented the proposed method, tested it on real radio frequency (RF) circuits, and show that the method gives great MT performance on 4-core and 8-core computers.