Mapping DSP Algorithms into FPGA

Author

Maslennikow, Oleg ; Sergiyenko, Anatolij

Author_Institution

Tech. Univ. of Koszalin

fYear

2006

fDate

13-17 Sept. 2006

Firstpage

208

Lastpage

213

Abstract

A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs

Keywords

data flow graphs; digital signal processing chips; field programmable gate arrays; pipeline processing; DSP algorithm; FPGA device; digital signal processing; event subspace; field programmable gate array; multidimensional index space; multiplexer input; pipelined data path; synchronous data flow graph; Clocks; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Flow graphs; Hardware; Multidimensional systems; Multiplexing; Processor scheduling; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on

Conference_Location

Bialystok

Print_ISBN

0-7695-2554-7

Type

conf

DOI

10.1109/PARELEC.2006.51

Filename

1698662

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2586481