Fabrication Of 0.06 /spl mu/m Poly-si Gate Using Duv Lithography With A Designed Si/sub x/O/sub y/N/sub z/ Film As An Arc And Hardmask

Author

Wei W.Lee ; Qizhi He ; Hanratty, M. ; Rogers, D. ; Chatterjee, A. ; Kraft, R. ; Chapman, R.A.

Author_Institution

Texas Instruments, Semiconductor Process and Device Center, MS944, PO Box 655621, Dallas, TX 75243

fYear

1997

fDate

10-12 June 1997

Firstpage

131

Lastpage

132

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-75-1

Type

DOI

10.1109/VLSIT.1997.623733

Filename

623733

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