Modeling metal dishing for interconnect optimization

Author

Runzi Chang ; Yu Cao ; Spanos, C.J.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2003

fDate

8-10 Dec. 2003

Abstract

An analytical dishing model is developed for the damascene process, based on experimental data and physical analysis. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is favorable when the dishing radius is less than 50 /spl mu/m. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is 2-4 from both efficiency and performance considerations.

Keywords

circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; semiconductor process modelling; 50 micron; damascene process; dishing effect suppression; dishing radius; interconnect optimization; metal dishing modeling; process improvement; uniform wide line splitting; Analytical models; Chemical technology; Copper; Dielectrics; Electrical resistance measurement; Integrated circuit interconnections; Semiconductor device measurement; Shape measurement; Surface resistance; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269267

Filename

1269267