Dopant redistribution effects in preamorphized silicon during low temperature annealing

Author

Venezia, V.C. ; Duffy, R. ; Pelaz, L. ; Aboy, M. ; Heringa, Anco ; Griffin, P.B. ; Wang, C.C. ; Hopstaken, M.J.P. ; Tamminga, Y. ; Dao, T. ; Pawlak, B. ; Roozeboom, F.

Author_Institution

Philips Res. Leuven, Belgium

fYear

2003

fDate

8-10 Dec. 2003

Abstract

The time evolution of B, As, and In doping profiles during and after solid phase epitaxial regrowth (SPER) was monitored for conditions applicable to sub-65 nm CMOS technologies. As and In segregate during SPER by a sweep of the regrowing interface. In the case of B, significant B diffusion in a-Si occurs during SPER, while afterwards B uphill diffusion dominates. With the aid of atomistic simulation we have identified a temperature dependent time to maximum uphill B diffusion.

Keywords

CMOS integrated circuits; annealing; arsenic; boron; diffusion; doping profiles; elemental semiconductors; indium; segregation; semiconductor process modelling; silicon; solid phase epitaxial growth; 65 nm; CMOS technologies; SPER; Si:As; Si:B; Si:In; a-Si; diffusion; dopant redistribution effects; dopant segregation; doping profile time evolution; low temperature annealing; preamorphized silicon; regrowing interface sweep; solid phase epitaxial regrowth; uphill diffusion temperature dependent time; Annealing; Atomic layer deposition; CMOS technology; Condition monitoring; Doping profiles; High-K gate dielectrics; Silicon; Solids; Surface resistance; Temperature dependence;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269328

Filename

1269328