• DocumentCode
    2590353
  • Title

    Modified reduced delay BCD adder

  • Author

    Sundaresan, C. ; Chaitanya, C.V.S. ; Venkateswaran, Dr PR ; Bhat, Dr Somashekara ; Kumar, J.M.

  • Author_Institution
    MCIS, Manipal Univ., Manipal, India
  • Volume
    4
  • fYear
    2011
  • fDate
    15-17 Oct. 2011
  • Firstpage
    2148
  • Lastpage
    2151
  • Abstract
    Current trends in the academia and industry is managing and processing a high volume of data. Most of the time is spend on converting the data from decimal to binary, processing and converting back to decimal. The direct production of decimal sum offers a significant improvement in addition over methods requiring decimal correction. Here is the proposition which will reduce the conversion and processing time. This work is the extension of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. In some corner case, adder design was misbehaving and has been corrected and presented.
  • Keywords
    adders; binary codes; database management systems; medical computing; binary coded decimal adder; data management; data processing; decimal correction; decimal sum; modified reduced delay BCD adder; Adders; Computers; Delay; Educational institutions; Hardware; Simulation; Software; Adder; BCD Adder; Carry lookahead adder; Higher Valence adder; decimal adder;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Biomedical Engineering and Informatics (BMEI), 2011 4th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-9351-7
  • Type

    conf

  • DOI
    10.1109/BMEI.2011.6098679
  • Filename
    6098679