DocumentCode
2590426
Title
Compositional memory systems for multimedia communicating tasks
Author
Molnos, A.M. ; Heijligers, M.J.M. ; Cotofana, S.D. ; van Eijndhoven, J.T.J.
Author_Institution
Delft Univ. of Technol., Netherlands
fYear
2005
fDate
7-11 March 2005
Firstpage
932
Abstract
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other´s data out of the cache in an unpredictable manner In this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive. This paper proposes a new method that imposes compositionality to the system´s performance and makes different memory hierarchy optimizations possible for multimedia communicating tasks when running on embedded multiprocessor architectures. The method is based on a cache allocation strategy that assigns sets of the unified cache exclusively to tasks and to the communication buffers. We also analytically formulate the problem and describe a method to compute the cache partitioning ratio for optimizing the throughput and the consumed power. When applied to a multiprocessor with memory hierarchy our technique delivers also performance gain. Compared to the shared cache case, for an application consisting of two jpeg decoders and one edge detection algorithm 5 times less misses are experienced and for an mpeg2 decoder 6.5 times less misses are experienced.
Keywords
cache storage; circuit optimisation; edge detection; logic partitioning; memory architecture; multimedia communication; multiprocessing systems; parallel processing; video coding; cache allocation strategy; cache data; cache models; cache partitioning ratio; communication buffers; compositional memory systems; consumed power optimization; decoder misses; edge detection algorithm; embedded multiprocessor architecture; jpeg decoders; memory hierarchy optimization; mpeg2 decoder; multimedia communicating tasks; multiprocessor memory hierarchy; real-time parallel processing; system performance; task integration; throughput optimization; unified cache set assignment; Computer architecture; Decoding; Multimedia communication; Multimedia systems; Optimization methods; Parallel processing; Predictive models; Real time systems; System performance; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2005. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2288-2
Type
conf
DOI
10.1109/DATE.2005.99
Filename
1395705
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