Integration of fluorinated nano-crystal memory cells with 4.6F/sup 2/ size by landing plug polysilicon contact and direct-tungsten bitline

Author

Il-Gweon Kim ; Yanagidaira, K. ; Hiramoto, T.

Author_Institution

Inst. of Ind. Sci., Univ. of Tokyo, Japan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

This paper reports the first full process integration of nano-crystal memory (NCM) with 4.6F/sup 2/ cell (size: 0.0777 /spl mu/m/sup 2/) based on NOR type, which is achieved by landing plug polysilicon contact (LPC) and direct tungsten (W) bitline (BL). Robust 4-threshold voltage (VT) states for 2 bits operation per cell are verified. Also, the comparable characteristics to NCM with conventional silicide BL contact are obtained and NCM reliability is significantly improved by properly fluorinated effect while still keeping process compatibility and controllability, which is the only alternative for volume manufacture of high density NCM.

Keywords

elemental semiconductors; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit reliability; integrated memory circuits; nanocontacts; nanoelectronics; nanostructured materials; silicon; tungsten; 2 bit; NCM characteristics; NCM reliability; NOR type cell size; Si; W; direct-tungsten bitline; fluorinated nano-crystal memory cell integration; high density NCM; landing plug polysilicon contact; nano-crystal memory; process compatibility; process controllability; process integration; robust four-threshold voltage states; silicide BL contact; volume manufacture; Chemicals; Controllability; Fabrication; Linear predictive coding; Lithography; Plugs; Silicides; Silicon compounds; Stress; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269354

Filename

1269354