Fully integrated 50 Gbit/s half-rate linear phase detector in SiGe BiCMOS

Summary form only given, as follows. Presented is a fully integrated half-rate linear phase detector for clock and data recovery (CDR) in serial communication systems which is capable of operating up to 50 Gbit/s. Because of its half-rate architecture, the phase detector features inherent 1:2 demultiplexing. At a core supply voltage of 3.3 V and a bias voltage of 3.6 V, the total power consumption of the integrated circuit amounts to 1.22 W. Using a 0.25 µm SiGe HBT BiCMOS process, the chip core area occupies 0.88mm².